As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin-like field effect transistor (FinFET). A typical FinFET is fabricated with a thin ‘fin’ extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. It is beneficial to have a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow.
There have been problems associated with fabrication of FinFETs. For example, the process of growing epitaxial (epi) silicon on portions of the fin as part of source and drain features has been adversely impacted by various process parameters of current fabrication techniques. Therefore, what is desired an improved method of growing epi silicon in semiconductor fabrication.